Case study · M.S. capstone · 2026

Finding defect patterns on semiconductor wafers

Two models for a chip fab. The first recognizes defect patterns on wafer maps, including mixed patterns where several faults overlap. The second estimates the chance that a production run fails, from its sensor readings, before anyone tests the wafers.

Context

Capstone for an M.S. in Computer Science, AI and machine learning

Data

MixedWM38 wafer maps; UCI SECOM process sensor data

Methods

Prototypical network (few-shot learning) for wafer maps; probabilistic classification for sensor data

Model

Four convolution blocks of 64 filters, a 576-number embedding, 113,088 parameters

Try it

The trained model runs live on the home page. The code is private.

The problem

After electrical testing, every die on a wafer is marked pass or fail. Plotted as a map, the failures often form shapes: a ring around the edge, a scratch, a cluster near the center. Each shape points back to a different step in the process, so naming the pattern quickly tells an engineer where to look.

Real wafers rarely show one clean pattern. The MixedWM38 dataset reflects that. It holds about 38,000 wafer maps on a 52 by 52 grid, labeled across 38 classes, and most of those classes are combinations of two, three, or four basic defect types layered on the same wafer.

The second model works earlier in the line. The SECOM dataset records 1,567 production runs from a real fab, each with about 590 sensor readings. Only 104 of those runs failed, many readings are missing, and some sensors never change at all.

Constraints

• Defect classes in a fab aren’t fixed. A new failure signature can appear with only a handful of labeled examples.
• SECOM’s imbalance makes plain accuracy a misleading score, so evaluation had to focus on the failures.

Decisions

What broke

Early on, I set up the training loop wrong. I’d estimated about 50,000 operations, and the loop as written came to nearly 2.5 billion. Normally I watched results come in as training ran, but this time I hadn’t set that up, so all I saw was a run that usually took a minute or two still going after fifteen. I killed it, traced the problem to the epoch loop, and rewrote it. Now I build plenty of metrics into my programs and models, so progress, and problems, show up right away.

The harder part was conceptual. Episodic training was new to me, and it took a lot of diagrams and metaphors before it clicked. The one that worked was a substitute teacher. After covering so many different classes and subjects, a good substitute can walk into a room they’ve never seen and still make a solid guess at the answer to a student’s question. Episodic training builds that kind of experience: thousands of small, different classrooms instead of one class all year.

What the model taught me

Building the live demo exposed a shortcut. In MixedWM38, normal wafers never have more than 14.5% of their dies failed, and every patterned wafer has at least 15%. The model learned to use that difference: extra random noise on a normal wafer reads as Edge-loc, and a pattern drawn on a perfectly clean wafer often goes unnoticed. The test score never showed this, because every test wafer came from the same dataset.

My fix would be an explicit failure-rate cutoff. If a pattern needs a minimum share of failed dies before it can be read at all, anything below that share is most likely random noise, so the rule can say so directly instead of the model learning it silently. In this dataset a 10% cutoff wouldn’t misfile a single patterned wafer. In a real fab, the threshold would have to come from production data, where a small scratch on a quiet wafer could fall under it.

Results

• 97.6% test accuracy on 5-way, 5-shot episodes from the five classes the model never trained on (300 fixed episodes). Validation: 96.7%. Before tuning, the baseline scored 96.4% and 95.3%.
• Tuning also made training about 60% faster, from 73.8 to 29.4 seconds. I cut training from 10,000 episodes to 2,500, and widened each one from 5 classes to 20. Fewer episodes alone dropped validation accuracy to 90.6%; the wider episodes brought it back above the baseline.
• 89.0% when choosing among all 38 classes at once, as the live demo does, and 80.4% on the ten never-seen classes.
• The hardest classes mix Edge-loc with Scratch or Loc, at 55 to 60% in the 38-way setting.
• 0.725 ROC AUC for the sensor model on the test set, up from 0.656 for the baseline, and balanced error fell from 44.1% to 33.5%. I scored it this way instead of on accuracy because only 6.6% of runs fail. The test set held just 21 failures, so 5-fold cross-validation gives a steadier read: 0.640 AUC and 36.3% balanced error. UCI lists cross-validated balanced error rates of 33.5 to 40.1% for six reference methods on this dataset, and mine falls inside that range.

What I’d do next

If this were going into a real fab, I’d start with the noise cutoff. MixedWM38 puts the line at 15%, but the real threshold should come from the fab’s own production data, where quiet wafers and small patterns may not look like the dataset.

For the sensor model, I’d benchmark the Bayesian network against black-box models and measure more than accuracy: how quickly engineers can act on what each model tells them. A model that scores a little lower but points straight at sensor 431 could still get a fix in faster. That comparison is the real test of the tradeoff in ADR 03.

Once it’s serving, I’d monitor for drift. Processes change, and when wafers stop looking like the prototypes, the model should flag it instead of quietly guessing. The few-shot design helps here: when a new pattern shows up, five labeled wafers are enough to add it.